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lc 2 mos 16-bit voltage output dac ad7846 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2000C2010 analog devices, inc. all rights reserved. features 16-bit monotonicity over temperature 2 lsbs integral linearity error microprocessor compatible with readback capability unipolar or bipolar output multiplying capability low power (100 mw typical) functional block diagram a2 a1 a3 16 segment switch matrix r r r 12-bit dac dac latch i/o latch control logic ad7846 r 21 4 7 8 9 6 5 23 22 25 24 r v ref? v ref+ v ss dgnd clr ldac r/w cs v out r in v dd v cc 4 12 12 db15 db0 08490-001 10 3 20 figure 1. general description the ad7846 is a 16-bit dac constructed with the analog devices, inc., lc 2 mos process. it has v ref+ and v ref? reference inputs and an on-chip output amplifier. these can be configured to give a unipolar output range (0 v to +5 v, 0 v to +10 v) or bipolar output ranges (5 v, 10 v). the dac uses a segmented architecture. the four msbs in the dac latch select one of the segments in a 16-resistor string. both taps of the segment are buffered by amplifiers and fed to a 12-bit dac, which provides a further 12 bits of resolution. this architecture ensures 16-bit monotonicity. excellent integral linearity results from tight matching between the input offset voltages of the two buffer amplifiers. in addition to the excellent accuracy specifications, the ad7846 also offers a comprehensive microprocessor interface. there are 16 data i/o pins, plus control lines ( cs , r/ w , ldac and clr ). r/ w and cs allow writing to and reading from the i/o latch. this is the readback function, which is useful in ate applications. ldac allows simultaneous updating of dacs in a multi-dac system and the clr line will reset the contents of the dac latch to 00000 or 10000 depending on the state of r/ w . this means that the dac output can be reset to 0 v in both the unipolar and bipolar configurations. the ad7846 is available in 28-lead plastic, ceramic, and plcc packages. product highlights 1. 16-bit monotonicity the guaranteed 16-bit monotonicity over temperature makes the ad7846 ideal for closed-loop applications. 2. readback the ability to read back the dac register contents minimizes software routines when the ad7846 is used in ate systems. 3. power dissipation power dissipation of 100 mw makes the ad7846 the lowest power, high accuracy dac on the market.
ad7846 rev. g | page 2 of 24 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac performance characteristics ................................................ 4 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 10 ? circuit description ......................................................................... 11 ? digital section ............................................................................. 11 ? digital-to-analog conversion .................................................. 11 ? output stage ................................................................................ 12 ? unipolar binary operation ........................................................... 13 ? bipolar operation ........................................................................... 14 ? multiplying operation ............................................................... 14 ? position measurement application .............................................. 15 ? microprocessor interfacing ........................................................... 16 ? ad7846-to-8086 interface ........................................................ 16 ? ad7846-to-mc68000 interface ............................................... 16 ? digital feedthrough ....................................................................... 17 ? application hints ........................................................................... 18 ? noise ............................................................................................ 18 ? grounding ................................................................................... 18 ? printed circuit board layout ................................................... 18 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 22 ? revision history 4/10rev. f to rev. g change to figure 1 ........................................................................... 1 12/09rev. e to rev. f updated format .................................................................. universal changes to table 4 ............................................................................ 6 deleted other output voltage ranges section ............................ 9 deleted figure 20 and table 5; renumbered sequentially ......... 9 deleted test application section and figure 21 ........................ 10 deleted figure 29 to figure 31 ...................................................... 14 changes to printed circuit board layout section ..................... 18 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 22
ad7846 rev. g | page 3 of 24 specifications v dd = +14.25 v to +15.75 v; v ss = ?14.25 v to C15.75 v; v cc = +4.75 v to +5.25 v. v out loaded with 2 k, 1000 pf to 0 v; v ref+ = +5 v; r in connected to 0 v. all specifications t min to t max , unless otherwise noted. table 1. parameter 1 j, a versions k, b versions unit test conditions/comments resolution 16 16 bits unipolar output v ref? = 0 v, v out = 0 v to +10 v relative accuracy at +25c 12 4 lsb typ 1 lsb = 153 v t min to t max 16 8 lsb max differential nonlinearity error 1 0.5 lsb max all grades guaranteed monotonic gain error at +25c 12 6 lsb typ v out load = 10 m t min to t max 16 16 lsb max offset error at +25c 12 6 lsb typ t min to t max 16 16 lsb max gain tc 2 1 1 ppm fsr/c typ offset tc 2 1 1 ppm fsr/c typ bipolar output v ref? = C5 v, v out = ?10 v to +10 v relative accuracy at +25c 6 2 lsb typ 1 lsb = 305 v t min to t max 8 4 lsb max differential nonlinearity error 1 0.5 lsb max all grades guaranteed monotonic gain error at +25c 6 4 lsb typ v out load = 10 m t min to t max 16 16 lsb max offset error at +25c 6 4 lsb typ v out load = 10 m t min to t max 16 12 lsb max bipolar zero error at +25c 6 4 lsb typ t min to t max 12 8 lsb max gain tc 2 1 1 ppm fsr/ctyp offset tc 2 1 1 ppm fsr/ctyp bipolar zero tc 2 1 1 ppm fsr/ctyp reference input input resistance 20 20 k min resistance from v ref+ to v ref? 40 40 k max typically 30 k v ref+ range v ss + 6 to v ss + 6 to v min to v dd ? 6 v dd ? 6 v max v ref? range v ss + 6 to v ss + 6 to v min to v dd ? 6 v dd ? 6 v max output characteristics output voltage swing v ss + 4 to v ss + 4 to v max v dd ? 3 v dd ? 3 resistive load 2 2 k min to 0 v capacitive load 1000 1000 pf max to 0 v output resistance 0.3 0.3 typ short circuit current 25 25 ma typ to 0 v or any power supply digital inputs v ih (input high voltage) 2.4 2.4 v min v il (input low voltage) 0.8 0.8 v max i in (input current) 10 10 a max c in (input capacitance) 2 10 10 pf max
ad7846 rev. g | page 4 of 24 parameter 1 j, a versions k, b versions unit test conditions/comments digital outputs v ol (output low voltage) 0.4 0.4 v max i sink = 1.6 ma v oh (output high voltage) 4.0 4.0 v min i source = 400 a floating state leakage current 10 10 a max db0 to db15 = 0 to v cc floating state output capacitance 2 10 10 pf max power requirements 3 v dd +11.4/+15.75 +11.4/+15.75 v min/v max v ss ?11.4/?15.75 ?11.4/?15.75 v min/v max v cc +4.75/+5.25 +4.75/+5.25 v min/v max i dd 5 5 ma max v out unloaded i ss 5 5 ma max v out unloaded i cc 1 1 ma max power supply sensitivity 4 1.5 1.5 lsb/v max power dissipation 100 100 mw typ v out unloaded 1 temperature ranges as follows: j, k versions: 0c to +70c; a, b versions: ?40c to +85c. 2 guaranteed by design and characterization, not production tested. 3 the ad7846 is functional with power su pplies of 12 v. see the typical pe rformance characteristics section. 4 sensitivity of gain error, offset error, and bipolar zero error to v dd , v ss variations. ac performance characteristics these characteristics are included for design guidance and are not subject to test. v ref+ = +5 v; v dd = +14.25 v to +15.75 v; v ss = ?14.25 v to ?15.75 v; v cc = +4.75 v to +5.25 v; r in connected to 0 v, unless otherwise noted. table 2. parameter limit at t min to t max (all versions) unit test conditions/comments output settling time 1 6 s max to 0.006% fsr, v out loaded, v ref? = 0 v, typically 3.5 s 9 s max to 0.003% fsr, v out loaded, v ref? = C5 v, typically 6.5 s slew rate 7 v/s typ digital-to-analog glitch impulse 70 nv-sec typ dac alternately loaded with 100000 and 011111, v out unloaded ac feedthrough 0.5 mv p-p typ v ref? = 0 v, v ref+ = 1 v rms, 10 khz sine wave, dac loaded with all 0s digital feedthrough 10 nv-sec typ dac alternately loaded with all 1s and all 0s. cs high output noise voltage density, 1 khz to 100 khz 50 nv/hz typ measured at v out , dac loaded with 011101111, v ref+ = v ref? = 0 v 1 ldac = 0. settling time does not in clude deglitching time of 2.5 s (typ).
ad7846 rev. g | page 5 of 24 timing characteristics v dd = +14.25 v to +15.75 v, v ss = ?14.25 v to ?15.75 v, v cc = +4.75 v to +5.25 v, unless otherwise noted. table 3. parameter 1 limit at t min to t max (all versions) unit test conditions/comments t 1 0 ns min r/ w to cs setup time t 2 60 ns min cs pulse width (write cycle) t 3 0 ns min r/ w to cs hold time t 4 60 ns min data setup time t 5 0 ns min data hold time t 6 2 120 ns max data access time t 7 3 10 ns min bus relinquish time 60 ns max t 8 0 ns min clr setup time t 9 70 ns min clr pulse width t 10 0 ns min clr hold time t 11 70 ns min ldac pulse width t 12 130 ns min cs pulse width (read cycle) 1 timing specifications are sample tested at +25 c to ensure compliance . all input control signals are specified with t r = t f = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 t 6 is measured with the load circui ts of figure 3 and figure 4 and de fined as the time required for an output to cross 0.8 v or 2 .4 v. 3 t 7 is defined as the time required for an output to change 0.5 v when loaded wi th the circuits of figure 5 and figure 6. db0 to db15 5v t 3 t 1 t 3 data valid data valid t 11 t 10 ldac clr cs r/w 0v 5v 0v 5v 0v 5v 0v 5v 0v t 10 t 8 t 9 t 6 t 1 t 8 t 9 t 4 t 5 t 7 t 12 t 2 0 8490-006 figure 2. timing diagram dbn 3k? 100pf dgnd 0 8490-002 figure 3. load circuit for access time (t 6 )?high z to v oh dbn 100pf 3k? dgnd 5 v 08490-003 figure 4. load circuits for bus relinquish time (t 6 )?high z to v ol dbn 3k? 10pf dgnd 08490-004 figure 5. load circuit for access time (t 7 )?high z to v oh dbn 10pf 3k? dgnd 5 v 08490-005 figure 6. load circuits for bus relinquish time (t 7 )?high z to v ol
ad7846 rev. g | page 6 of 24 absolute maximum ratings table 4. parameter rating v dd to dgnd ?0.4 v to +17 v v cc to dgnd ?0.4 v, v dd + 0.4 v, or +7 v (whichever is lower) v ss to dgnd +0.4 v to ?17 v v ref+ to dgnd v dd + 0.4 v, v ss ? 0.4 v v ref? to dgnd v dd + 0.4 v, v ss ? 0.4 v v out to dgnd 1 v dd + 0.4 v, v ss ? 0.4 v, or 10 v (whichever is lower) r in to dgnd v dd + 0.4 v, v ss ? 0.4 v digital input voltage to dgnd ?0.4 v to v cc + 0.4 v digital output voltage to dgnd ?0.4 v to v cc + 0.4 v power dissipation (any package) to +75c 1000 mw derates above +75c 10 mw/c operating temperature range j, k versions 0c to +70c a, b versions ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering) +300c 1 v out can be shorted to dgnd, v dd , v ss , or v cc provided that the power dissipation of the package is not exceeded. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7846 rev. g | page 7 of 24 pin configurations and function descriptions top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad7846 db11 db12 db13 db14 db15 db2 db1 db0 v dd v cc v ss v out v ref+ v ref? r in db10 db9 db8 db7 db6 dgnd db3 db4 db5 ldac r/w cs clr 08490-007 figure 7. pdip pin configuration 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 ldac clr cs r/w dgnd db6 v out v ref+ v ref? r in v ss db15 db14 v dd db0 db1 db2 db3 db4 db5 db13 db12 db11 db10 db9 db8 db7 ad7846 v cc 08490-008 figure 8. cerdip pin configuration table 5. pin function descriptions pin mnemonic description 1 to 3 db2 to db0 data i/os. db0 is lsb. 4 v dd positive supply for analog circ uitry. this is +15 v nominal. 5 v out dac output voltage. 6 r in input to summing resistor of dac output amplifier. this is used to select output voltage ranges. see table 6 . 7 v ref+ v ref+ input. the dac is specified for v ref+ = +5 v. 8 v ref? v ref? input. for unipolar operation connect v ref? to 0 v, and for bipolar operation connect it to ?5 v. the device is specified for both conditions. 9 v ss negative supply for the analog circuitry. this is ?15 v nominal. 10 to 19 db15 to db6 data i/os. db15 is msb. 20 dgnd ground for digital circuitry. 21 v cc positive supply for digital circuitry. this is +5 v nominal. 22 r/ w r/ w input. this pin can be used to load data to the dac or to read back the dac latch contents. 23 cs chip select input. this pin selects the device. 24 clr clear input. the dac can be cleared to 000000 or 100000. see table 7 . 25 ldac asynchronous load input to dac. 26 to 28 db5 to db3 data i/os. table 6. output voltage ranges output range v ref+ v ref? r in 0 v to +5 v +5 v 0 v v out 0 v to +10 v +5 v 0 v 0 v +5 v to ?5 v +5 v ?5 v v out +5 v to ?5 v +5 v 0 v +5 v +10 v to ?10 v +5 v ?5 v 0 v
ad7846 rev. g | page 8 of 24 typical performance characteristics 1v 2mv 20s ?0.40v a1 08490-009 figure 9. ac feedthrough, v ref+ = 1 v rms, 10 khz sine wave frequency (hz) v out (mv p-p) 0 100 2 1k 10k 100k 1m 4 6 1 3 5 7 8 v dd = +15v v ss = ?15v v ref + = +1v rms v ref ? = 0v 08490-010 figure 10. ac feedthrough to v out vs. frequency frequency (hz) 30 0 10 100 1k 10k 100k 1m 10m 20 10 5 25 15 v out (v p-p) v dd = +15v v ss = ?15v v ref+ = 5v sine wave v ref? = 0v gain = +2 08490-011 figure 11. large signal frequency response frequency (hz) noise spectral density (nv/ hz) 0 100 100 1k 10k 100k 1m 200 300 400 50 150 250 350 450 500 v ref+ = v ref? = 0v gain = +1 dac loaded with all 1s 08490-012 figure 12. noise spectral density 50mv/div 5v/div 0.5s/div data v out 0 8490-013 figure 13. digital-to-analog glitch impulse without internal deglitcher (10000 to 011111 transition) 50mv/div 5v/div data 5v/div ldac 1s/div v out 0 8490-014 figure 14. digital-to-analog glitch impulse with internal deglitcher (10000 to 011111 transition)
ad7846 rev. g | page 9 of 24 10v 5v 2s 0v a1 v ref + , 5v v out + , 10v 08490-015 figure 15. pulse response (large signal) 1s 0.025v a1 100mv 50mv v ref + , 50mv v out + , 100mv 08490-016 figure 16. pulse response (small signal) start 100.0hz rbw 3hz ref 2.24v 10db/div marker 442.0hz 1.70v stop 2000.0hz st 422 sec range 3.98v vbw 10hz 08490-017 figure 17. spectral response of digitally constructed sine wave v dd , v ss (v) inl (lsb) 0.5 11 12 13 14 15 1.0 1.5 2.0 2.5 3.0 3.5 4.0 16 t a = +25c v ref+ = +5v v ref? = 0v gain = +1 0 8490-018 figure 18. typical integral nonlinearity vs. v dd /v ss v dd , v ss (v) dnl (lsb) 0 11 12 13 14 15 0.1 0.3 0.2 0.4 0.5 0.7 0.6 0.9 0.8 1.0 16 t a = +25c v ref+ = +5v v ref? = 0v gain = +1 0 8490-019 figure 19. typical differential nonlinearity vs. v dd /v ss
ad7846 rev. g | page 10 of 24 terminology least significant bit this is the analog weighting of 1 bit of the digital word in a dac. for the ad7846, 1 lsb = (v ref+ ? v ref? )/2 16 . relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for both endpoints (that is, offset and gain errors are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal change between any two adjacent codes. a specified differential nonlinearity of 1 lsb over the operating temperature range ensures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output with all 1s loaded after offset error has been adjusted out. gain error is adjustable to zero with an external potentiometer. offset error this is the error present at the device output with all 0s loaded in the dac. it is due to op amp input offset voltage and bias current and the dac leakage current. bipolar zero error when the ad7846 is connected for bipolar output and 10000 is loaded to the dac, the deviation of the analog output from the ideal midscale of 0 v is called the bipolar zero error. digital-to-analog glitch impulse this is the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-sec or nv-sec depending upon whether the glitch is measured as a current or a voltage. multiplying feedthrough error this is an ac error due to capacitive feedthrough from either of the v ref terminals to v out when the dac is loaded with all 0s. digital feedthrough when the dac is not selected (that is, cs is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the v out pin. this noise is digital feedthrough.
ad7846 rev. g | page 11 of 24 circuit description digital section figure 20 shows the digital control logic and on-chip data latches in the ad7846. table 7 is the associated truth table. the digital- to-analog converter (dac) has two latches that are controlled by four signals: cs , r/ w , ldac , and clr . the input latch is connected to the data bus (db15 to db0). a word is written to the input latch by bringing cs low and r/ w low. the contents of the input latch can be read back by bringing cs low and r/ w high. this feature is called readback and is used in system diagnostic and calibration routines. data is transferred from the input latch to the dac latch with the ldac strobe. the equivalent analog value of the dac latch contents appears at the dac output. the clr pin resets the dac latch contents to 000000 or 100000, depending on the state of r/ w . writing a clr loads 000000 and reading a clr loads 100000. to reset a dac to 0 v in a unipolar system, the user should assert clr while r/ w is low; to reset to 0 v in a bipolar system, assert the clr while r/ w is high. r/ w clr cs db15 db0 16 16 16 dac db15 rst db15 set db14 to db0 rst 3-state i/o latch db15 to db0 latches ldac 08490-020 figure 20. input control logic tale 7. control logic truth tale cs r/ w ldac clr function 1 x x x 3-state dac i/o latch in high-z state 0 0 x x dac i/o latch loaded with db15 to db0 0 1 x x contents of dac i/o latch available on db15 to db0 x x 0 1 contents of dac i/o latch transferred to dac latch x 0 x 0 dac latch loaded with 000000 x 1 x 0 dac latch loaded with 100000 digital-to-analog conversion figure 21 shows the digital-to-analog section of the ad7846. there are three dacs, each of which has its own buffer amplifiers. dac1 and dac2 are 4-bit dacs. they share a 16-resistor string but have their own analog multiplexers. the voltage reference is applied to the resistor string. dac3 is a 12-bit voltage mode dac with its own output stage. the four msbs of the 16-bit digital code drive dac1 and dac2, and the 12 lsbs control dac3. using dac1 and dac2, the msbs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of dac3. this dac interpolates between these two voltages to produce the analog output voltage. to prevent nonmonotonicity in the dac due to amplifier offset voltages, dac1 and dac2 leap along the resistor string. for example, when switching from segment 1 to segment 2, dac1 switches from the bottom of segment 1 to the top of segment 2 while dac2 stays connected to the top of segment 1. the code driving dac3 is automatically complemented to compensate for the inversion of its inputs. this means that any linearity effects due to amplifier offset voltages remain unchanged when switching from one segment to the next and 16-bit monotonicity is ensured if dac3 is monotonic. thus, 12-bit resistor matching in dac3 guarantees overall 16-bit monotonicity. this is much more achievable than 16-bit matching, which a conventional r-2r structure needs.
ad7846 rev. g | page 12 of 24 s1 v ref+ v ref? dac1 segment 1 segment 16 s3 s15 s17 s16 s14 s4 s2 dac2 dac3 12-bit dac db11 to db0 db15 to db12 db15 to db12 r r v out r in a3 a2 a1 08490-021 figure 21. digital-to-analog conversion output stage the output stage of the ad7846 is shown in figure 22 . it is capable of driving a 2 k/1000 pf load. it also has a resistor feedback network that allows the user to configure it for gains of 1 or 2. table 6 shows the different output ranges that are possible. an additional feature is that the output buffer is configured as a track-and-hold amplifier. although normally tracking its input, this amplifier is placed in a hold mode for approximately 2.5 s after the leading edge of ldac . this short state keeps the dac output at its previous voltage while the ad7846 is internally changing to its new value. thus, any glitches that occur in the transition are not seen at the output. in systems where the ldac is tied permanently low, the deglitching is not in operation. and show the outputs of the ad7846 without and with the deglitcher. figure 13 figure 14 c1 ldac v out r in dac3 one shot 10k ? 10k ? 08490-022 figure 22. output stage
ad7846 rev. g | page 13 of 24 unipolar binary operation figure 23 shows the ad7846 in the unipolar binary circuit configuration. the dac is driven by the ad586 +5 v reference. because r in is tied to 0 v, the output amplifier has a gain of 2 and the output range is 0 v to +10 v. if a 0 v to +5 v range is required, r in should be tied to v out , configuring the output stage for a gain of 1. tabl e 8 gives the code table for the circuit of figure 23 . r in v out dgnd +15 v +5 v v cc v dd v ref+ v ref? r1 10k ? c1 1f signal ground ?15v *additional pins omitted for clarity ad7846* ad586 v out (0v to +10v) v ss 2 5 4 67 21 5 20 6 4 8 8 08490-023 figure 23. unipolar binary operation table 8. code table for figure 23 binary number in dac latch msb lsb 1 analog output v ot 1111 1111 1111 1111 +10 (65,535/65,536) v 1000 0000 0000 0000 +10 (32,768/65,536) v 0000 0000 0000 0001 +10 (1/65,536) v 0000 0000 0000 0000 0 v 1 lsb = 10 v/2 16 = 10 v/65,536 = 152 v. offset and gain can be adjusted in figure 23 as follows: ? to adjust offset, disconnect the v ref? input from 0 v, load the dac with all 0s, and adjust the v ref? voltage until v out = 0 v. ? for gain adjustment, the ad7846 should be loaded with all 1s and r1 adjusted until v out = 10 (65,535)/(65,536) = 9.999847 v. if a simple resistor divider is used to vary the v ref? voltage, it is important that the temperature coefficients of these resistors match that of the dac input resistance (?300 ppm/c). otherwise, extra offset errors are introduced over temperature. many circuits do not require these offset and gain adjustments. in these circuits, r1 can be omitted. pin 5 of the ad586 can be left open circuit and pin 8 (v ref? ) of the ad7846 tied to 0 v.
ad7846 rev. g | page 14 of 24 bipolar operation figure 24 shows the ad7846 set up for 10 v bipolar operation. the ad588 provides precision 5 v tracking outputs that are fed to the v ref+ and v ref? inputs of the ad7846. the code table for figure 24 is shown in table 9 . dgnd +15 v +5 v v dd v ss v cc v out r in v ref+ v ref? r2 10k ? c1 1f signal ground ?15v * additional pins omitted for clarity ad7846* ad588 v out (?10v to +10v) +15v ?15v r3 100k ? r1 39k ? +15 v 4 21 9 5 6 20 7 2 3 1 14 15 16 13 8 12 11 10 5 9 7 46 8 0 8490-024 figure 24. bipolar 10 v operation table 9. offset binary code table for figure 24 binary number in dac latch msb lsb 1 analog output v ot 1111 1111 1111 1111 +10 (32,767/32,768) v 1000 0000 0000 0001 +10 (1/32,768) v 1000 0000 0000 0000 0 v 0111 1111 1111 1111 ?10 (1/32,768) v 0000 0000 0000 0000 ?10 (32,768/32,768) v 1 lsb = 10 v/2 15 = 10 v/32,768 = 305 v. full-scale and bipolar zero adjustment are provided by varying the gain and balance on the ad588. r2 varies the gain on the ad588 while r3 adjusts the +5 v and ?5 v outputs together with respect to ground. for bipolar zero adjustment on the ad7846, load the dac with 100000 and adjust r3 until v out = 0 v. full scale is adjusted by loading the dac with all 1s and adjusting r2 until v out = 9.999694 v. when bipolar zero and full-scale adjustment are not needed, r2 and r3 can be omitted, pin 12 on the ad588 should be connected to pin 11, and pin 5 should be left floating. if a user wants a 5 v output range, there are two choices. by tying pin 6 (r in ) of the ad7846 to v out (pin 5), the output stage gain is reduced to unity and the output range is 5 v. if only a positive 5 v reference is available, bipolar 5 v operation is still possible. tie v ref? to 0 v and connect r in to v ref+ . this also gives a 5 v output range. however, the linearity, gain, and offset error specifications are the same as the unipolar 0 v to 5 v range. multipling operation the ad7846 is a full multiplying dac. to obtain four-quadrant multiplication, tie v ref? to 0 v, apply the ac input to v ref+ , and tie r in to v ref+ . figure 11 shows the large signal frequency response when the dac is used in this fashion.
ad7846 rev. g | page 15 of 24 position measurement application figure 25 shows the ad7846 in a position measurement applica- tion using an linear variable displacement transducer (lvdt), an ad630 synchronous demodulator and a comparator to make a 16-bit lvdt-to-digital converter. the lvdt is excited with a fixed frequency and fixed amplitude sine wave (usually 2.5 khz, 2 v p-p). the outputs of the secondary coil are in antiphase and their relative amplitudes depend on the position of the core in the lvdt. the ad7846 output interpolates between these two inputs in response to the dac input code. the ad630 is set up so that it rectifies the dac output signal. thus, if the output of the dac is in phase with the v ref+ input, the inverting input to the compara- tor is positive, and if it is in phase with v ref? , the output is nega- tive. by turning on each bit of the dac in succession starting with the msb and deciding to leave it on or turn it off based on the comparator output, a 16-bit measurement of the core position is obtained. ad7846* lvdt db0 db15 r1 100k ? c1 1f processor data bus signal ground to processor port *additional pins omitted for clarity x asin t ?(1?x) asin t a sin t ad630* dgnd v out r in v ref+ v ref? 6 20 7 5 8 10 13 10 9 16 3 08490-027 figure 25. ad7846 in position measurement application
ad7846 rev. g | page 16 of 24 microprocessor interfacing ad7846-to-8086 interface figure 26 shows the 8086 16-bit processor interfacing to the ad7846. the double buffering feature of the dac is not used in this circuit because ldac is permanently tied to 0 v. ad0 to ad15 (the 16-bit data bus) are connected to the dac data bus (db0 to db15). the 16-bit word is written to the dac in one mov instruction and the analog output responds immediately. in this example, the dac address is 0xd000. ad7846* +5v data bus cs ldac clr r/w db0 to db15 16-bit latch 8086 ale den rd wr ad0 to ad15 address decode address bus 08490-028 *linear circuitry omitted for clarity figure 26. ad7846-to-8086 interface circuit in a multiple dac system, the double buffering of the ad7846 allows the user to simultaneously update all dacs. in figure 27 , a 16-bit word is loaded to the input latches of each of the dacs in sequence. then, with one instruction to the appropriate address, cs4 (that is, ldac ) is brought low, updating all the dacs simultaneously. +5v data bus *linear circuitry omitted for clarity 16-bit latch address decode address bus ad7846* cs ldac r/w db0 to db15 8086 ale den rd wr ad0 to ad15 clr clr +5v clr +5v ad7846* cs ldac r/w db0 to db15 ad7846* cs ldac r/w db0 to db15 08490-029 figure 27. ad7846-to-8086 interface: multiple dac system ad7846-to-mc68000 interface interfacing between the ad7846 and mc68000 is accomplished using the circuit of figure 28 . the following routine writes data to the dac latches and then outputs the data via the dac latch. 1 000 move.w #w, d0 the desired dac dat a , w, is loaded into data register 0. w may be any value between 0 and 65535 (decimal) or 0 and ffff (hexadecimal). move.w d0, $ e000 the data, w, is transferred between d0 and the dac register. move.w trap # 228, d7 #14 control is returned to the system monitor using these two instructions. ad7846* +5v data bus cs ldac clr r/ w mc68000 ds dtack r/w a1 to a23 address decode address bus d0 to d15 db0 to db15 0 8490-030 * linear circuitry omitted for clarity figure 28. ad7846-to-mc68000 interface
ad7846 rev. g | page 17 of 24 digital feedthrough in the preceding interface configurations, most digital inputs to the ad7846 are directly connected to the microprocessor bus. even when the device is not selected, these inputs are constantly changing. the high frequency logic activity on the bus can feed through the dac package capacitance to show up as noise on the analog output. to minimize this digital feedthrough, isolate the dac from the noise source. figure 29 shows an interface circuit that isolates the dac from the bus. note that to make use of the ad7846 readback feature using the isolation technique of figure 29 , the latch needs to be bidirectional. ad7846* +5v data bus cs ldac clr micro- processor a1 to a15 address decode address bus d0 to d15 db0 to db15 r/w r/w 2 74ls245 b bus a bus dir g 08490-031 *linear circuitry omitted for clarity figure 29. ad7846 interface circuit using latches to minimize digital feedthrough
ad7846 rev. g | page 18 of 24 application hints noise in high resolution systems, noise is often the limiting factor. with a 10 v span, a 16-bit lsb is 152 v (C96 db). thus, the noise floor must stay below ?96 db in the frequency range of interest. figure 12 shows the noise spectral density for the ad7846. grounding as well as noise, the other prime consideration in high resolution dac systems is grounding. with an lsb size of 152 v and a load current of 5 ma, 1 lsb of error can be introduced by series resistance of only 0.03 . figure 30 shows recommended grounding for the ad7846 in a typical application. analog supply digital supply ?15v +15v 0v dgnd +5v signal ground ad7846* ad588* r1 r4 r l v out (+5v to ?5v) r2 r3 r5 * additional pins omitted for clarit y 2 9 16 4 9 21 20 6 5 1 3 7 8 15 14 08490-032 figure 30. ad7846 grounding r1 to r5 represent lead and track resistances on the printed circuit board. r1 is the resistance between the analog power supply ground and the signal ground. because current flowing in r1 is very low (bias current of ad588 sense amplifier), the effect of r1 is negligible. r2 and r3 represent track resistance between the ad588 outputs and the ad7846 reference inputs. because of the force and sense outputs on the ad588 , these resistances will also have a negligible effect on accuracy. r4 is the resistance between the dac output and the load. if r l is constant, then r4 introduces a gain error only that can be trimmed out in the calibration cycle. r5 is the resistance between the load and the analog common. if the output voltage is sensed across the load, r5 introduces a further gain error, which can be trimmed out. if, on the other hand, the output voltage is sensed at the analog supply common, r5 appears as part of the load and therefore introduces no errors. printed circuit board layout figure 31 shows the ad7846 in a typical application with the ad588 reference, producing an output analog voltage in the 10 v range. full-scale and bipolar zero adjustment are provided by potentiometer r2 and potentiometer r3. latches (2 74ls245) isolate the dac digital inputs from the active microprocessor bus and minimize digital feedthrough.
ad7846 rev. g | page 19 of 24 2 3 5 6 7 8 9 4 18 17 15 14 13 12 11 16 10 119 20 v out (+10v to ?10v) 2 3 5 6 7 8 9 4 18 17 15 14 13 12 11 16 10 119 20 c4/a4 c5/a5 c6/a6 c7/a7 c8/a8 c9/a9 c10/a10 c11/a11 c12/a12 c13/a13 c14/a14 c15/a15 c16/a16 c17/a17 c18/a18 c19/a19 c20/a20 c21/a21 c22/a22 c23/a23 c32/a32 c31/a31 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 ldac clr cs r/ w v out r in v ss v ref? v ref+ ad7846 j1 74ls245 74ls245 ad588 dgnd r2 100k ? c1 10f r3 100k ? r1 39k ? c12 1f c2 0.1f c4 0.1f c3 10f ?15v +15 v c5 10f c6 0.1f c7 0.1f +5v +5v 18 17 16 15 14 13 12 11 10 21 4 7 3 264 7 5 10 11 12 813 9 1 14 15 16 8 9 20 6 5 19 26 27 28 22 23 24 25 1 2 3 08490-033 figure 31. schematic for ad7846 board
ad7846 rev. g | page 20 of 24 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 28 11 4 15 0.610 (15.49) 0.500 (12.70) 0.005 (0.13) min 0.100 (2.54) max 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225(5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 15 0 pin 1 030106-a figure 32. 28-lead ceramic dual in-line package [cerdip] (q-28-2) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole leads. compliant to jedec standards ms-011 071006-a 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.050 (1.27) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 11 4 15 figure 33. 28-lead plastic dual in-line package [pdip] wide body (n-28-2) dimensions shown in inches and (millimeters)
ad7846 rev. g | page 21 of 24 1 28 5 11 18 botton view 19 25 26 4 12 0.15 (3.81) ref 0.075 (1.91) ref 0.028 (0.71) 0.022 (0.56) 0.300 (7.62) ref 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) ref 0.020 (0.51) min 0.05 (1.27) 0.095 (2.41) 0.075 (1.90) 0.458 (11.63) 0.442 (11.23) sq 0.458 (11.63) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 022106-a figure 34. 28-terminal cerami c leadless chip carrier [lcc] (e-28-1) dimensions shown in inches and (millimeters) compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508-a figure 35. 28-lead plastic leaded chip carrier [plcc] (p-28) dimensions shown in inches and (millimeters)
ad7846 rev. g | page 22 of 24 ordering guide model 1 temperature range relative accuracy package description package option 5962-89697013a ?55c to +125c 16 lsb 28-terminal ce ramic leadless chip carrier [lcc] e-28-1 5962-8969701xa ?55c to +125c 16 lsb 28-lead ceramic dual in-line package [cerdip] q-28-2 ad7846jn 0c to +70c 16 lsb 28-lead pl astic dual in-line package [pdip] n-28-2 ad7846jnz 0c to +70c 16 lsb 28-lead plas tic dual in-line package [pdip] n-28-2 ad7846kn 0c to +70c 8 lsb 28-lead plastic dual in-line package [pdip] n-28-2 ad7846knz 0c to +70c 8 lsb 28-lead plastic dual in-line package [pdip] n-28-2 ad7846jp 0c to +70c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846jp-reel 0c to +70c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846jpz 0c to +70c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846jpz-reel 0c to +70c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846kp 0c to +70c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846kp-reel 0c to +70c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 AD7846KPZ 0c to +70c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 AD7846KPZ-reel 0c to +70c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846ap ?40c to +85c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846apz ?40c to +85c 16 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846aq ?40c to +85c 16 lsb 28-lead ceramic dual in-line package [cerdip] q-28-2 ad7846bp ?40c to +85c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846bpz ?40c to +85c 8 lsb 28-lead plastic leaded chip carrier [plcc] p-28 ad7846achips ?40c to +85c 16 lsb die 1 z = rohs compliant part.
ad7846 rev. g | page 23 of 24 notes
ad7846 rev. g | page 24 of 24 notes ?2000C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08490-0-4/10(g)

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